Intel Director discusses the new architecture that will power all the flagship devices

Intel recently introduced the new architecture that will feature in their new offerings. The company believes that this will push the envelope of performance of not only Intel’s processors, but also usher in a new era of computing for the years to come. We, at Techplugged, got a unique opportunity to have a discussion with Ahmed Ibrahim, Director, Sales Enablement – Service Providers EMEA, Intel, where we spoke a bit more about this new architecture and what Intel plans to do with it going forward. Here is the transcript of our enlightening conversation.

 

 

1. Could you provide a brief list of the new offerings and shed some light on the motivation behind creating this new architecture?

The demand for more compute performance is endless and customer workloads are larger, more complex, and more diverse than ever before. Staying ahead of this demand and constantly breaking barriers when it comes to technology is at the heart of Intel. 

While graphics are not new territory for Intel, we have reinvigorated our efforts to build a scalable microarchitecture to support a range of graphics processing applications. This Architecture Day, we revealed two new x86 core architectures; our first performance hybrid architecture, ‘Alder Lake’ with the intelligent Intel Thread Director workload scheduler; “Sapphire Rapids,” the next-generation Intel Xeon Scalable processor for the data center; new infrastructure processing units; and upcoming graphics architectures, including the Xe HPG and Xe HPC microarchitectures, and Alchemist and Ponte Vecchio SoCs.

These new architectures will power upcoming high-performance products and establish the foundations for the next era of Intel innovation aimed at meeting the world’s ever-growing demand for more computing power.

Please find a brief list of all the new offerings below: 

• x86 Efficient-core: designed for throughput efficiency and enabling scalable multithreaded performance for modern multitasking
• x86 Performance-core: designed for speed and pushes the limits of low latency and single-threaded application performance
• Alder Lake Client SoC: Intel’s first performance hybrid architecture which integrates both efficient-core and performance-core
• Intel Thread Director: ensuring both performance-core and efficient-core work seamlessly 
• X^e HPG Microarchitecture: powers the Alchemist family of SoCs
• X^eSS: deliver novel upscaling technology that enables high-performance and high-fidelity visuals 
• Sapphire Rapids: delivers substantial compute performance across dynamic and increasingly demanding data center usages and is workload-optimized to deliver high performance on elastic compute models. The new built-in acceleration engine includes: 
  • Intel Accelerator Interfacing Architecture (AIA) 
  • Intel Advanced Matrix Extensions (AMX)
  • Intel Data Streaming Accelerator (DSA) 
• Infrastructure Processing Unit (IPU): programmable networking device designed to enable cloud and communication service providers to reduce overhead and free up performance CPUs 
• Mount Evans: architected and developed together with a top cloud service provider and integrates learnings from multiple generations of FPGA SmartNICs
• Oak Springs Canyon: the industry’s leading FPGA in power, efficiency, and performance
• Intel N6000 Acceleration Development Platform (Arrow Creek): designed for use with Xeon-based servers 
• Ponte Vecchio: delivers industry-leading FLOPs and compute density to accelerate AI, high-performance computing (HPC), and advanced analytics workloads
• one API: provides an open, standards-based unified software stack that is cross-architecture and cross-vendor, allowing developers to break free from proprietary languages and programming models

 

2. Can you talk to us a bit more about the new x86 architecture in comparison to what we have in the market today?

With its Efficient-core and Performance-core, Intel signals the biggest architectural shift in a generation for x86 central processing units. The Efficient-core microarchitecture is designed for throughput efficiency and efficient offloading of background tasks for multitasking. It runs at low voltage and creates headroom to increase the frequency and ramp up performance for more demanding workloads. 

Whereas the Performance-core microarchitecture is designed for speed, the highest performing CPU core Intel has built. It pushes the limits of low latency and single-threaded application performance and provides a significant boost at high-power efficiency that can better support large applications.

3. We have noticed how Intel-powered computers are progressively pushing the envelope when it comes to getting a slimmer hardware profile. But, with a slimmer profile come to a host of challenges that hamper intense applications such as graphic-intensive games and design tools. Will the new generation of Intel processors help optimize these activities in slimmer laptops? 

Intel’s next-generation client architecture, code-named “Alder Lake,” is the company’s first performance hybrid architecture. Alder Lake integrates a Performance-core and an Efficient-core to provide significant performance across all workload types. For the cores to work seamlessly with the operating system, Intel developed Intel Thread Director, built directly into the core. The  Thread Director empowers the operating system to place the right thread on the right core at the right time. We are confident that Alder Lake will deliver performance that scales to support all client segments from ultra-portable laptops to enthusiast and commercial desktops.

4. Could you tell us a bit more about Ponte Vecchio in layman’s terms? This will help the newcomers understand and appreciate what the platform is all about. 

Ponte Vecchio uses a variety of process technologies, demonstrating our vision of the future in the best way possible. It is Intel’s first GPU based on the X^eHPC microarchitecture that will be used with our next generation of Xeon Scalable ‘Sapphire Rapids’ processors. This will be one of the industry’s first supercomputers to feature over 1 ExaFLOPS FP64 performance. 

Ponte Vecchio is comprised of several complex designs that manifest in tiles, which are then assembled through an energy management information base (EMIB) tile that enables a low-power, high-speed connection between the tiles. These are put together in Foveros packaging that creates the 3D stacking of active silicon for power and interconnects density. A high-speed MDFI interconnect allows scaling from one to two stacks.

Below is a little description of all the tiles that make up Ponte Vecchio: 

• Compute Tile: dense package of X^ecores and is the heart of Ponte Vecchio 
• Base Tile: connective tissue of Ponte Vecchio – it is a large die built on Intel 7 optimized for Foveros technology 
• XeLink Tile: provides the connectivity between GPUs supporting eight links per tile 

Ponte Vecchio will be released in 2022 for HPC and AI markets. 

5. Will the new architecture also play a role in smartphones, or will the focus remain on laptops for now?

Looking back at the past year, technology was at the heart of how we all communicated, worked, played, and coped through the pandemic. Enormous computing power proved crucial.  Moving forward, we will face a massive demand for computing – potentially a 1,000x need by 2025, which is an x1,000 boost in four years in Moore’s Law to the power of five.

Our CEO, Pat Gelsinger, also an architect, stated at this year’s Architecture Day, “We face daunting compute challenges that can only be solved through revolutionary architectures and platforms. Our talented architects and engineers made possible all this technology magic.”

The world is counting on architects and engineers to solve the most difficult computational problems, to enrich people’s lives. Our strategy and execution are accelerating to meet these demands.